Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

In this article, a complementary metal-oxide-semiconductor (CMOS) frequency and duty cycle controller (FDCC) is presented for on-chip signal synthesis. The circuit consists of a few logic gates and a voltage-controlled oscillator, and is functionally similar to a programmable divide-by-N frequency divider. It is designed for driving integrated sensor and actuator systems. Compared with other frequency dividers with the same control flexibility, the proposed circuit features a compact topology and allows the control over the output signal duty cycle. For the proof-of-concept, a prototype 1× 4 array of identical FDCCs has been fabricated on a 0.35 μm Austria Mikro Systeme (AMS) CMOS process. Each FDCC occupies an active area of 0.0051 mm, which is area-efficient. The array has been validated to generate 4 synchronized 4 MHz ∼ 64 MHz outputs with a duty cycle tunning range of 3.125% ∼ 96.875%. Although driven by a 5-V power supply, it still provides a relatively high power-efficiency of 1.26 GHz/mW .


Introduction
In the past decades, for the merit of cost, power consumption and size reduction, considerable efforts have been made on developing integrated sensor and actuator platforms.For such advanced systems, clock and signal sources play an important role for performing diverse analog, digital, mixed-signal functions and driving sensors/transducers.These sources usually operate simultaneously but require dedicated optimizations for the desired performance.As a result, clock generators of integrated platforms are typically implemented as combinations of several independent on-chip phase-locked loops (PLLs) [1,2] and/or delay-locked loops (DLLs) [3,4].However, the design of PLLs and DLLs requires special expertise and multiple of these circuit blocks, while providing high quality domains, inevitably complicates the system and can become costly solutions.
Therefore, clock multiplication from one clean reference is preferred.Elkholy et al. reported a multi-output all-digital clock generator based on open-loop delta-sigma (∆Σ) fractional dividers [5], and there are high-performance dividers that can potentially be implemented for clock multiplication [6,7,8].
However, none of these offers tunable duty cycle, which is useful for transducer/sensor excitation and control [9,10,11], clock duty cycle calibration, non-overlap signal generation [12] and circuit energy-saving controls [13], etc.
On the other hand, open-loop digitally controlled oscillators (DCOs) can provide tunable duty cycle [14,15,16].However, due to inevitable frequency mismatches, enormous efforts are required to synchronize multiple DCOs and allow multiphase generation.Furthermore, these open-loop DCOs are vulnerable to process-voltage-temperature (PVT) variations.
In view of these drawbacks, we propose the design methodology of an onchip CMOS FDCC for clock generation/multiplication purposes.By introducing simple circuit blocks to delicately control the oscillation, a relaxation oscillator is enabled to operate in an open-loop manner with enhanced mismatch and 2 PVT tolerance.The FDCC is functionally similar to a programmable divideby-N frequency divider.Compared with traditional programmable dividers for clock multiplication, the proposed FDCC can provide tunable duty cycle that is required by many integrated sensor and actuator systems.It is also comparatively power-and area-efficient.Compared with traditional open-loop DCOs, it is robust against PVT variations and allows the generation of multiphase.
The FDCC is designed for driving integrated systems such as ultrasonic capsule endoscopy system [10], integrated acoustic imager and tweezer system [11], gas detection system [9,12] and flow sensing system [13], etc.It is compact and highly flexible and hence is also favored by prototyping systems.
Rest of this article is organized as follows.In Section 2, the proposed FDCC architecture is presented, followed by a digitally controlled FDCC in Section 3. The simulation and measurement results of a prototype 1 × 4 FDCC array, including the demonstration of functionality and its performance against PVT variations, are presented in Sections 4&5.The main contributions of this article are listed as follows: 1) An FDCC design methodology for on-chip signal synthesis is proposed.
The FDCC is compact, flexible, power-and area-efficient and is designed for driving integrated systems and prototyping circuits/systems.
2) The simulation and experimental results of an FDCC implemented in a 0.35 µm AMS process are presented for the validation of the design methodology.This FDCC only occupies an active area of 0.0051 mm 2 and is capable of generating 4M Hz ∼ 64M Hz outputs with 3.125% ∼ 96.875% duty cycles.Although driven by a 5-V power supply, it still provides a relatively high power efficiency of 1.26 GHz/mW in comparison with other frequency dividers [5,6,17,18,19,20,21].
3) A digitally controlled FDCC is proposed and examined with simulations based on a 2-V , 0.18 µm Taiwan Semiconductor Manufacturing Company (TSMC) process.The area occupation of this FDCC is 0.001 mm 2 and the power efficiency reaches 4.41.It can generate 3.125% ∼ 96.875% duty-cycle 46.875M Hz ∼ 750M Hz square waves.

PROPOSED FREQUENCY DIVISION AND DUTY CYCLE CON-TROL CIRCUIT
A CMOS relaxation oscillator architecture is shown in Figure 1 [22].It consists of a charge pump, a Schmitt trigger [23] and an inverter.By tuning V biasp and/or V biasn the signal frequency and duty cycle of the output can be tuned.If (1) is fulfilled, the output signal frequency f o can be estimated as (2).
where V dd is the supply voltage; V tp is the PMOS threshold voltage and V tn is the NMOS threshold voltage in a specific CMOS process; V lt and V ut are the lower and upper threshold voltages of the Schmitt trigger, respectively; C 1 is the capacitance of capacitor Cap1 in Figure 1; C OX is the gate oxide capacitance per unit area; µ p and µ n are the effective mobilities of charge-carriers in PMOS and NMOS devices, respectively; W P 1 and L P 1 are the gate width and length of the PMOSFET, P 1; and W N 1 and L N 1 are the gate width and length of the NMOSFET, N 1.
The FDCC proposed in this article is based on an original idea of quantizing the charging and discharging processes of Cap1 in oscillation.As a result, a transmission gate is added to the oscillator structure as a quantizer that is controlled by the clock signal CLK, forming the clock-controlled oscillator (CCO) shown in Figure 2.Only when CLK turns on the transmission gate, Cap1 can get charged/discharged.In theory, once CLK is fixed, the output is related to it by a factor that can be precisely defined with V biasp and V biasn .
However, the same V biasp and V biasn values can result in different oscillation

Output V biasn Charge Pump Schmitt Trigger Inverter
Figure 1: Schematic of a CMOS relaxation oscillator [22].
frequencies between any two of the fabricated CCOs.This is due to device mismatch/variations.Particularly, P 1/N 1 variations can cause different capacitor charging/discharging rates, and P 3 ∼ P 5&N 3 ∼ N 5 mismatches can result in different Schmitt trigger threshold voltages [23].An example of the mismatched oscillations between two fabricated CCOs (CCO1&CCO2) is shown in Figure 2 (b).
To cope with the mismatch, an over-charging circuit is first added, as illustrated in Figure 3 (a).Note that the transmission gate is replaced by P 7 and In this case, V biasp is obtained from the current sources in DAC1.Assuming 150 P 0 in Figure 6 shares the same size with P 1 in Figure 5, for a charging period covers i (i = 1, 2, . . ., n) CLK cycles (i charging levels/steps), the current I p i should theoretically be designed to fulfill: where V ut2 is the upper threshold voltage of ST2; f CLK is the CLK signal frequency and should be a fixed value; and a ±5% variation is allowed for the 155 thresholds, which is conservative enough for most CMOS processes.And the corresponding V i biasp range can be calculated as: It can be seen from ( 3) that I p i is allowed in a wider range if C 1 V ut2 is larger, which also relates to an improved PVT tolerance.Furthermore, I p i can be designed as the mid-point of its boundaries to provide an optimized performance: The current I n k for designing DAC2 can be derived by replacing V ut2 with (V dd − V lt2 ), where k is the number of discharging levels/steps; V lt2 is the lower threshold voltage of ST2.
Note that the DAC noise has to be taken into consideration.Use DAC1 as an example, if the peak-to-peak amplitude of its noise is higher than the minimum voltage range of V i biasp calculated from (4) (corresponding to the maximum value of i in a specific design), either a DAC architecture with low intrinsic noise or DAC noise shaping techniques should be introduced.

Frequency division with programmable modulus and output duty cycle control
Frequency division with programmable integral modulus can be directly achieved with the circuit shown in Figure 6.By adjusting V biasp and/or V biasn with DACs, the output signal frequency and duty cycle are tuned.The frequency division modulus (N ) and output signal duty cycle can be calculated as: This is the same as setting V biasp and V biasn to be: Furthermore, if 50% duty cycle is required for odd moduli, the architecture in Figure 7 can be implemented.

Programmable fractional division
Fractional-N division can be realized by dithering the modulus of the architecture in Figure 6 with a Σ∆ modulator.Noting that the tuning of V biasp should only be done when the output signal is at logic low level, so that the frequency is switched without generating unintended waveforms.On the other hand, the tunning of V biasn should be done in the complimentary manner.A digital-to-time converter [5] can be adopted to improve the phase noise and jitter performance, with the digitally controlled FDCC operating as a multi modulus divider.

Simulation results
The architecture in Figure 5 was implemented on a 5-V , 0.35-µm AMS CMOS process (Table 1) to form a 1 × 4 FDCC array, and the layout of which was simulated with a Monte Carlo (MC) approach in Cadence.Clocked at 128 M Hz, V biasp and V biasn were tuned to allow a divide-by-16 operation with 50% output signal duty cycle.The results of 100 instances of MC simulation are illustrated in Figure 8, which demonstrates the performance of the FDCC against process variations.
Out1 ∼ 4 waveforms correspond to the output signals from the four FDCCs  operation.Higher gate-to-source voltages could then be applied to P1 and N1, which improve the matching performance between current mirrors in different AND gates that control P2 and N2.
From (3), it is clear that a larger C 1 , V ut2 , a higher CLK frequency and a lower duty cycle can enhance the tolerance of the FDCC to process variations, generally because these lead to a larger charging current for any fixed modulus.
The digitally controlled FDCC architecture in Figure 6 was then simulated with a TSMC 0.18 µm CMOS process design kit.Specifications of the FDCC and DACs are given in Table 1 and 2, respectively.An MC approach was used to find I p i and I n k values that allow a consistent output in 200 instances of MC simulation for i, k = 5, 6, 7, 8. Generally, these values compare higher than the theoretical values determined with (5), and this is mainly due to the parasitic capacitors extracted from the layout.

ASIC fabrication and experiment setup
The prototype IC was fabricated on a 0.35 µm CMOS Process at AMS.For validation, test points and additional buffers were set around the circuit, with the 440 × 80 µm 2 structure at the center of the chip forming the 1 × 4 array, including the FDCCs and row selecting logics, as shown in Figure 9.The output buffer set on-chip allows the ASIC to provide 5 V square waves with 1 mA drive current and ∼ 5 pF output load capacitance.
In order to fully explore the FDCC architecture, the methodology presented in Section 3 was not implemented in this prototype and bias voltage signals V biasp and V biasn were directly supplied through a precision source/measure unit (B2912A, Keysight technologies).CLK signal was obtained from a PLL 230 device (NB3N502, ON Semiconductor) set on a printed circuit board (PCB) test bench, forming a multi-output signal generator/clock like the architectures presented in [5,14,15].

Electrical testing of the ASIC
To test the frequency division performance, a 128 M Hz clock was firstly      The same testing method was implemented for various power supply voltages and operating temperatures, with results shown in Figure 13.For this prototype, the real upper and lower thresholds of ST2 can be calculated as V r ut2 ≈ 0.6V dd + 0.4V tn − 0.2|V tp | and V r lt2 ≈ 1.25V tn + 0.125|V tp | − 0.125V dd , respectively [23].Hence, +0.5 V change on V dd results in about +0.3V change on upper threshold and about −0.06 V change on lower threshold.On the other hand, small V tn and |V tp | variations introduced by temperature change are negligible, which meets the output behavior illustrated in Figure 13.For enhanced tolerance, a high-performance Schmitt trigger architecture may be implemented.Table 3 shows the performance summary and comparison to prior frequency dividers.
The proposed FDCC offers tunable duty cycle while maintaining high power efficiency and small area occupation.It is also suitable for driving systems that require high-voltage signals (2 ∼ 5 V ) for transducer excitation, such as acoustic tweezers and imagers.For improved operating frequency, a smaller feature size can be adopted.

Conclusion
This article has reported the design methodology of a CMOS FDCC.The

Figure 7 :
Figure 7: Schematic of an FDCC for 50% duty cycle odd moduli divisions.

Figure 8 :
Figure 8: The simulated result of the prototype 1 × 4 FDCC array clocked at 128 M Hz (CLK); Out1 ∼ 4 are the output waveforms from per-FDCC output pads and Cap1 ∼ 4 are the potentials on per-FDCC capacitors.

5 .
Experimental setup and test results

Figure 9 :
Figure 9: Photomicrograph of the prototype 1×4 FDCC array and detailed layout of an FDCC.

235
Figure 10 (c) and Figure 10 (d) demonstrate the instantaneous switching of the output frequency, from 9.14 M Hz to 8.53 M Hz and 8 M Hz, respectively. 245

Features
of the proposed FDCC are further demonstrated in Figure12.In

Figure 12 (Figure 11 :
Figure 12 (a), the number of charging levels is shown as a function of V biasp .The data was obtained by determining the span/range of V biasp that can synchronize all four output signals at virous input and output frequencies, corresponding to

Figure 12 :
Figure 12: (a) The number of charging levels vs. V biasp values.(b) The number of discharging levels vs. V biasn values.Each point represents a voltage span of 5-mV .

Figure 13 :
Figure 13: (a) The number of charging levels vs. V biasp values and (b) the number of discharging levels vs. V biasn values for various supply voltages.(c) The number of charging levels vs. V biasp values and (d) the number of discharging levels vs. V biasn values for various operating temperatures.

5. 3 .
Towards the integration with piezoelectric micromachined ultrasonic transducers (PMUTs)In order to further demonstrate the functionality of the prototype FDCC array, a PMUT matrix[24] consists of a 2 × 2 arrangement of acoustic elements was introduced to form an acoustic tweezer.Each element of the PMUT matrix contains nine diaphragms operating at 8 M Hz, as shown in Figure14 (a).The four acoustic elements were driven by four synchronized 8-M Hz, 5-V pp unipolar square waves generated from the FDCC array, sending out acoustic waves.To shape the acoustic field, the four FDCCs in the array were set to start at different times (with the help of Reset), so that the four signals generated were with different phases.The vibration of the acoustic elements was recorded with a laser Doppler vibrometer, as shown in Fig. Figure 14 (b)&(c).Obvious deflections and four phase quadrants can be clearly observed, which is sufficient to demonstrate acoustic field shaping and the functional potential of PMUTs and FDCCs integration.

Figure 14 :
Figure 14: Vibration intensity and phase recorded with a laser vibrometer.
use of such FDCC provides an extra tool of synthesizing signals for systemon-chips and integrated sensor and actuator systems.It also opens up a new way of implementing relaxation oscillator with simple and open-loop topology, which can benefit academic prototyping particularly.Combined with DACs, the proposed FDCC can be implemented as a programmable fractional divider or a digitally controlled FDCC, which allows the control of output duty cycle and the generation of multiphase.A prototype FDCC array has been implemented in a 5-V , 0.35-µm CMOS process.The simulated and experimental results have demonstrated its functionality and shown its performances against PVT variations.

Table 1 :
Specifications of the FDCCs

Table 2 :
Specifications of the digital-to-analog converters

Table 3 :
Performance summary and comparisons **DAC included