Parametric study of pulsed laser deposited (PLD) WSe2 2D transistors

A fabrication process for making large area transistors on pulsed laser deposited (PLD) WSe 2 has been developed. Large films of WSe 2 have been deposited via PLD technique on SiO 2 /Si substrate. Employing a mask-less lithography technique and using vapour XeF 2 as an etchant, transistors of lengths (17, 83, 323 and 1000 µm) and widths (14 and 850 µm) have been fabricated. Electrical characterization of the transistors show that as the channel length (L) decreases, the magnitude of the drain-source current increases. In addition, the current across the transistor has been found to increase by increasing the channel width (W). Moreover, channels with large areas have been found to deliver substantially more drain-source current compared with smaller channel areas with similar W/L. A W/L ratio of 0.85 has been found to possess the highest drain current across the transistors fabricated. From the transfer length measurement (TLM), the sheet resistance and contact resistance of the device have been measured. Field effect mobility of the transistors have been calculated. Raman spectrum shows that PLD WSe 2 possess similar quality as exfoliated WSe 2 . However, Photoluminescence (PL) spectrum and TLM results suggest the lack of bandgap in our 14-layer PLD WSe 2 .


INTRODUCTION
Since 2004 when thin carbon films (single layer graphene) were produced by exfoliation and their electric properties studied [1], two dimensional (2D) materials have continued to gain attention in an effort to discover better materials as well as to expand their applications [2].Beyond graphene with its overlapping band structure [1], other materials have been investigated such as the transition metal dichalcogenide (TMD).TMD are materials with layered structures that can be cleaved down to less than 100nm.TMD's have gained prominence by virtue of their unique electrical and optical properties.Electrically, they range from insulators (HfS2) through to semiconductors (WSe2), semi metals (WTe2) and to metals (VSe2).The diversity of TMD is attributed to the existence of non-bonding d-bands and the degree to which they are filled [3].
According to Sahin et al. [4], the band gap of semiconducting TMD increases and transforms to a direct band gap with decreasing number of layers, which makes them promising candidates for nanoscale field-effect transistors and solar cell applications [5].The lack of covalent bonding between TMD layers enables the fabrication of hetero-structures by allowing the stacking of materials.The structural plane of WSe2 consists of two atoms of selenium and one atom of tungsten covalently bonded together (Se-W-Se).These atoms form a hexagonal arrangement and adjacent planes are held together by van der waals interactions [6].As a result of the layered stacking, the scotch tape method has been employed to transfer WSe2 at various thicknesses and within a few square-microns in area onto a substrate.The flakes being of several layers thick, have been etched using xenon difluoride (XeF2) vapour [7].However, one disadvantage associated with exfoliated materials is that after exfoliation, materials transferred to a substrate are distributed randomly across the substrate and are of various thicknesses and dimensions.The non-uniformity both in thickness and in dimension makes it difficult to achieve complex fabrication designs like hetero-structure devices.The size of the 2D material is of importance especially in IC design and the need to control the material thickness over large area has paved the way for bottom up deposition techniques.Pulsed laser deposition (PLD) [8], chemical layer deposition (CVD) [9] and atomic layer deposition (ALD) [10] have all been employed in growing 2D materials for larger area, controlling the material thickness and improving the quality of film produced.PLD, like CVD is a bottom-up deposition technique.PLD allows for large area growth (>2 cm) of 2D materials with control in sample thickness and size.On the other hand, although exfoliation produces purer layers, it is not possible to control the size and thickness.The inability to control sample size and thickness during exfoliation is inherent in the deposition process.PLD has not been researched widely for the fabrication of 2D materials.Technically, the PLD process is a simplified bottom-up deposition technique as it requires no additional precursors except the target of the deposited material [8].PLD technique is relatively quick and samples can be grown within 30 minutes.Also, the samples can be grown at low temperatures at around 450 C.CVD requires high temperature (750 -1000 C), longer process time and additional precursors [11].Moreover, the thickness control for PLD is excellent as it is dependent on the number of laser pulses and it has short growth time thus possessing high repeatability [8], [12].Seo et.al [13], grew a centimetre scale monolayer of WSe2 thin film on SiO2/Si substrate via PLD.From their experiment, the PLD technique has been shown to achieve good layer uniformity and the thickness of the layer has been controlled by the number of laser pulses.However, other challenges exist in these bottom up approaches such as defect, domain size, and stoichiometry control [6].
In this work, we study the influence of the transistor channel dimensions on the electrical properties of the PLD WSe2 transistors.In addition, Raman and PL spectroscopy have been used to characterise the PLD WSe2.By employing photo-lithography and XeF2 vapour etching techniques, transistors with multiple channel dimensions have been fabricated.The channel dimension with optimum performance will be employed for future hetero-structure design.

Fabrication Process
WSe2 transistors have been designed and fabricated on a SiO2/Si substrate.Figure 1a shows the step by step fabrication process employed in making the PLD WSe2 transistors.Conventional photo-lithography technique has been employed to fabricate the device.Using a maskless lithography tool, several WSe2 channel patterns with lengths 17 µm, 83 µm, 323 µm and 1000 µm and width of 14 µm and 850 µm have been designed and fabricated.The WSe2 has been etched using vapour XeF2 (Orbis Alpha, MEMSTAR).During the vapour-etch, the chamber pressure has been maintained at 1.2 Torr.Nitrogen (N2) carrier on gas (100 sccm) flows over XeF2 crystal and transports the vapour XeF2 (25 sccm) onto the material.The etch rate recorded has been about 3 nm / min.The sample was etched completely within 3 minutes.Figure 1b shows the etched rectangular channel and a few alignment marks on a SiO2/Si substrate after the photoresist had been stripped off.To deposit the metal contacts (Titanium adhesion and Aluminium) on the channel, a sputtering tool (Plasmalab 400 OPT) has been used.20 nm of Titanium has been deposited at a rate of 3 nm/min and 300 nm of Aluminum has been deposited at 5.8 nm/min.The stack formed has been lifted-off using Microposit Remover 1165 (a photoresist remover) at 40°C.The stack has been immersed in the photo-resist stripper for about 2 hours before it was sonicated.The sonication lasted for about 15 seconds to remove the metal residue completely.The device has been rinsed in IPA and de-ionized water respectively.

Characterization
Raman spectroscopy, Energy Dispersive X-ray Spectroscopy (EDX) and Photoluminescence (PL) spectroscopy have been used to characterize the WSe2.The Raman and PL have been performed at room temperature and atmospheric pressure while the EDX has been performed in vacuum.EDX has been carried out using the Tescan Vega Scanning Electron Microscope (SEM).
To avoid heating or damage to the sample, 4 KV of HV has been applied for EDX.On the other hand, 5% of the 3 mW laser has been used for Raman and PL.The thickness of the WSe2 has been measured using the D5000 atomic force microscope (AFM).The measurement has been carried out in tapping mode with a tip of spring constant 3 N/m and resonant frequency of 75 KHz.
The electrical properties of the transistors have been tested using a Keithley probe station.The field effect behaviour has been investigated by back-gating the transistor from +50 to -130 V and the transfer characteristics plotted.From the transfer characteristics, the field effect mobility has been deduced.From the transfer length measurement, the sheet resistance and contact resistance of the devices have been measured.

AFM and EDX Analysis
To measure the thickness of the PLD WSe2 channel and the elemental composition of the sample, AFM and EDX analysis have been performed.The thickness of the WSe2 channel has been measured to be 10 nm ± 2 nm which is about 14-layer.The thickness of TMD materials can affect their optical and electrical response.Hence, it is important to compare the material thickness with its resultant properties [7], [13], [14].EDX analysis has been performed to detect the presence of impurity and discover the elemental composition of the material and substrate.The presence of impurity could affect the Raman and PL analysis as well as the electrical properties of the material.The EDX analysis is thus: Silicon 40.18%,Oxygen 39.57%, Tungsten 13.8% and Selenium 5.88%.This observation indicates the presence of W and Se on the substrate.to the top of the PLD WSe2 (b) the height profile of the PLD WSe2 sample is measured to be about 10 nm, which is about 14 layers of WSe2.The film has been found to be continuous across the substrate and possesses a surface roughness of approximately ±2 nm.In general, from a Raman spectrum, changes in the structural integrity (surface change or chemical bonding) of a material could be detected [15].As previously reported [7], exfoliated WSe2 crystals appear about the 250 cm -1 position on a Raman spectrum.Pulsed laser deposited WSe2 is expected to appear about the same region as has been reported [13].In-plane E 1 2g mode from the out-of-phase vibration and A1g mode from the out-of-plane vibrations of WSe2 both appear as a single peak (E 1 2g + A1g) at 252 cm -1 [7], [13], [15].From our samples, (E 1 2g + A1g) peak of PLD WSe2 appears at about the same peak position as exfoliated WSe2 as shown in figure 3a.Moreover in figure 3a, the presence of the B 1 2g peak indicates the sample is not a mono layer.Mono layer PLD WSe2 has only the primary Raman peaks E 1 2g + A1g [13]; same for exfoliated WSe2 [7].The presence of B 1 2g peak has been reported to be a result of interlayer interaction [8], [16].As the number of WSe2 layers increases, the Raman modes are expected to become more rigid resulting in vibrational softening [17].Therefore, the B 1 2g peak intensity is expected to diminish as the number of layers increases.The low intensity of the B 1 2g peak observed in our PLD WSe2, where there are 14 layers, could be due to the presence of vibrational dampening as a result of lower interlayer interaction [8], [16].In addition, the full width half maximum (FWHM) of exfoliated and CVD WSe2 have been extracted from literature.FWHM for exfoliated WSe2 have been measured to be 3.7 and 3.8 cm -1 for monolayer and bilayer respectively [7] while values of 4.2 and 5.5 cm -1 have been reported for monolayer CVD WSe2 [18], [19].The FWHM measured for our material is 15 cm -1 .Values of 12.45 and 14.23 cm -1 have been reported for mono layer and few (3) layers PLD WSe2 respectively [13].The FWHM measured in our experiment shows our 14-layer PLD WSe2 is of relatively good quality.

Analysis of the Raman and Photoluminescence (PL) Spectrum
Figure 3(b) shows the photoluminescence (PL) spectrum of our 14-layer PLD WSe2.The sample has been excited by a 450 nm laser.Normally, the PL spectrum of exfoliated WSe2 shows the Aexciton and trion peaks around the 750 -800 nm wavelength range [7].The bandgap of exfoliated and CVD WSe2 has been reported to be 1.65 eV and 1.6 eV respectively [7], [20].From the spectrum shown in figure 3(b), there is no noticeable PL peak at the A-exciton and trion region [21].The non-existence of the A-exciton and trion peaks suggests a lack of bandgap or the existence of non-radiative recombination in our PLD WSe2 [22].Also, the presence of grain boundaries can degrade the physical properties of 2D materials thus leading to quenching of the photoluminescence [23].Thicker WSe2 layers can result in a higher concentration of grain boundaries and subsequently the presence of quenching.Typically, monolayer thick (~0.7 nm) semiconducting TMDs are preferred as optoelectronic devices [24] due to the band gap increase as well as the transformation from indirect bandgap into a direct band gap with decreasing number of layers [25].

Electrical Properties
The electrical properties of the PLD WSe2 transistors fabricated have been characterised.

Transfer Length Measurement (TLM)
Using the TLM [26] technique as shown in figure 5(a), the sheet resistance  ℎ and contact resistance   of the 14-layer PLD WSe2 transistor have been calculated.The electrode probe spacing is 27 µm, 74 µm and 90 µm.From figure 5(b) above, the sheet resistance and contact resistance have been calculated to be 31.7 MΩ/□ and -6.11MΩ.µm respectively.Both the TLM and 4-point probe method produce negative contact resistance for PLD WSe2 at low gate voltage (-30 V to 30 V).As the gate voltage increases beyond 30 V, the polarity of the resistance changes.The negative contact resistance indicates the influence of metal-contact doping [27]- [29] and it occurs in materials with Dirac cone systems (no bandgap) [27].From the PL measurement in figure 3b, the lack of luminescence peak suggests our 14-layer PLD WSe2 has no bandgap.Hence, the negative contact resistance observed could be as a result of the lack of bandgap in the material.

Transfer Characteristics
The gated characteristics of the transistors fabricated on the PLD WSe2 has been studied.The influence of channel dimension (length 17 µm, 83 µm, 323 µm, 1000 µm and width 14 µm, 850 µm) on the drain-source current has been investigated and the field effect behaviour observed is shown in figure 6. Figure 6(a) shows the drain current ID against the back-gate voltage Vbg for channels with length (17 µm, 83 µm and 323 µm) and width of 14 µm.As the back-gate voltage Vbg has been varied from +50 to over -100V, there has been a continuous flow of current along the channel showing p-type behaviour, similar to p-channel depletion type MOSFET [30].It can be seen that as the channel length decreases, a higher drain-source current ID exists, probably because the channel resistance increases with increase in channel length.
Figure 6(b) shows the drain current ID against the back-gate voltage Vbg for channels with widths of (14 µm and 850 µm) and length 1000 µm.From the graph, it can be observed that as the channel width W increases, the drain-source current ID of the transistor is measured to increase.
The transistor with a channel width of 850 µm has a much larger current flowing across its channel probably due to a lower resistance.Drain-source current value of about 300 µA at -130 Vbg for a 7 nm thick exfoliated WSe2 has been reported by Chuang et.al [31] for a 0.3 µm long transistor channel.The relatively high ID value in their experiment is probably due to the very short channel and the high quality of exfoliated WSe2.
In addition, the drain current in figure 6 shows an exponential increase at Vbg greater than -100 V.This observation could be as a result of impact ionization [32] hence increasing the carrier density of the semiconductor.As a result, the current across the PLD WSe2 transistor increases dramatically.

Figure 7:
The graph shows the ID through the transistor against the ratio of the channel dimension (W/L).Channel dimensions with a width to length ratio of approximately 1 display higher values of ID through the device.
Figure 7 shows the drain current ID as a function of channel dimensions (W/L) of PLD WSe2 transistors for gate voltages up to -96 V.An exponential increase in ID is measured as the channel width to length ratio approaches 1.It can be seen that as the applied gate voltage increases, a more exponential increase in current is observed.From figure 7, channels 3 and 4 have similar dimension ratios but substantial variation in ID as the gate voltage increases.Channel 4 is about 850 µm by 1000 µm (W/L) in dimension making its area several times bigger than channel 3 which is 14 µm by 17.3 µm (W/L).The carrier density in both channels affects the flow of current across the transistor.It is expected that channels with larger area possess higher carrier density.However, in Channels 3 and 4, for W/L > 0.8, the area of the channel has been observed to have a much larger influence on the magnitude of ID across the device.
From figure 6a, the field effect mobility   of the semiconductor can be extracted using equation 1 [26].The capacitance of the oxide   =  0    ⁄ ; ℎ  = 300  between the channel and the back-gate.The   of 5.66 * 10 −2  2  −1  −1 has been measured from our 10 nm thick sample.The   in our experiment is higher than the value obtained for monolayer and few layers WSe2 thin films via PLD (5.28 * 10 −3  2  −1  −1 ) [13].The magnitude of the field effect mobility observed in 2D WSe2 could be influenced by interface screening and the presence of interlayer resistance [33].Interface roughness scattering present between the channel and the substrate could lower carrier mobility [34].The interface roughness effect is more prominent in monolayer channel as it is more sensitive to the substrate and the density change of the charge that exists in SiO2 [35].Thicker channels have a higher carrier mobility as the layers are further away from the SiO2 interface.Also, thicker layers have a relatively larger charge density compared to thinner layers that will serve to screen the effects of scattering from the interface [32].However, thicker WSe2 layers will have an interlayer resistance that may contribute to scattering.The existence of interlayer resistance across the layered separation of the channel should not pose serious concern since gating is expected to affect the bottom layers more [33].The carrier density for our 14layer PLD WSe2 has been calculated as 4.6 * 10 +16  −3 using the equation  = еµ and( =    −1   −1 ) [36].Similar values for carrier density have been calculated for single crystal WSe2 [37].According to Akinwande et.al, for transistor electronics, the optimum number of layers for better device parameters such as carrier mobility and contact resistance is unknown presently as several studies on 2D materials having different thicknesses have shown varied device performance [33], [38], [39].However, an average thickness of 10 nm for MoS2 and MoTe2 have been reported to possess higher carrier mobility than fewer layers or bulk samples [33], [34], [36].

CONCLUSION
In this study, we have fabricated large channel field effect transistors from 14-layer PLD WSe2 using a mask-less lithography technique and vapour XeF2 etching.The transistor performance has been investigated and the width has been found to have more influence on the device current than its length.A width to length ratio of 0.85:1 would be employed for future application.The field effect mobility in 14-layer PLD WSe2 has been calculated to be 5.66 * 10 −2  2  −1  −1 .
The AFM analysis shows the PLD WSe2 is about 10 nm thick and has a continuous film across the substrate.The Raman spectrum shows that the PLD WSe2 is of good quality and has not been affected by the fabrication process.The PL spectrum and TLM results from the PLD WSe2 suggest in its pristine form, the 14-layer PLD WSe2 possesses no bandgap.

Figure 1 :
Figure 1: (a) Schematic of the PLD WSe2 FET fabrication process; (b) PLD WSe2 channel and alignment mark pattern after etching using vapour XeF2.

Fig 2
Fig 2 show graphs obtained from the AFM experiments.(a) 7 µm by 7 µm AFM image of PLD WSe2 on SiO2 substrate.The grey line shows the step trace performed from the SiO2/Si substrate

Figure 3 :
Figure 3: (a) Raman spectrum of PLD WSe2.Active Raman peak at 252 cm -1 indicates good quality sample and the presence of B 1 2g secondary peak indicates multiple layers thick; (b) PL spectrum of PLD WSe2 shows the absence of an A-exciton and trion peak.

Figure 3 (
Figure3(a) shows the Raman spectrum of the sample which has been excited with a 450 nm laser.In general, from a Raman spectrum, changes in the structural integrity (surface change or chemical bonding) of a material could be detected[15].As previously reported[7], exfoliated WSe2 crystals appear about the 250 cm -1 position on a Raman spectrum.Pulsed laser deposited WSe2 is expected to appear about the same region as has been reported[13].In-plane E 1 2g mode from the out-of-phase vibration and A1g mode from the out-of-plane vibrations of WSe2 both appear as a single peak (E 1 2g + A1g) at 252 cm -1[7],[13],[15].From our samples, (E 1 2g + A1g) peak of PLD WSe2 appears at about the same peak position as exfoliated WSe2 as shown in figure3a.Moreover in figure3a, the presence of the B 1 2g peak indicates the sample is not a mono layer.Mono layer PLD WSe2 has only the primary Raman peaks E 1 2g + A1g[13]; same for exfoliated WSe2[7].The presence of B 1 2g peak has been reported to be a result of interlayer interaction[8],[16].As the number of WSe2 layers increases, the Raman modes are expected to become more rigid resulting in vibrational softening[17].Therefore, the B 1 2g peak intensity is expected to diminish as the number of layers increases.The low intensity of the B 1 2g peak observed in our PLD WSe2, where there are 14 layers, could be due to the presence of vibrational dampening as a result of lower interlayer interaction[8],[16].In addition, the full width half maximum (FWHM) of exfoliated and CVD WSe2 have been extracted from literature.FWHM for exfoliated WSe2 have been measured to be 3.7 and 3.8 cm -1 for monolayer and bilayer respectively[7] while values of 4.2 and 5.5 cm -1 have been reported for monolayer CVD WSe2[18],[19].The FWHM

Figure 4 (Figure 4 :
Figure 4: (a) Schematic of the fabricated PLD WSe2 FET with geometrical dimensions; (b) Actual device fabricated showing the PLD WSe2 channel with four metal electrodes on a SiO2 / Si substrate.

Figure 5 (
b) shows the electrode probe spacing against the measured total resistance for Vbg (24.5 V, -1.11 V and -26.7 V).

Figure 5b :
Figure 5b: Graph of total resistance as a function of electrode probe spacing plotted at various values of back-gate voltage showing a negative contact resistance at the y-intersect.